Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to an electrostatic discharge (ESD) circuit for protecting an internal circuit from ESD introduced thereinto.
In general, an ESD circuit is provided inside a semiconductor device, including a display driver IC (DDI), in order to protect an internal circuit from ESD. The ESD refers to a phenomenon that accumulated charges move between objects having different potentials at a high speed for several hundred pico seconds (ps) to several micro seconds (μs). As fabrication process technologies have recently been advanced, such ESD is so strong as to degrade an internal circuit under a situation in which the internal circuit is ultra-small in size. Hence, the importance of an ESD circuit tends to be emphasized.
Meanwhile, an ESD circuit is generally disposed between a pad and an internal circuit, and includes a normal diode, a bipolar junction transistor (BJT), a gate-grounded NMOS (GGNMOS), a gate-coupled NMOS (GCNMOS), and so on.
For reference, a GGNMOS has a structure in which a gate, a source, and a body are coupled to a ground voltage terminal. Due to a breakdown phenomenon, the internal structure of the GGNMOS operates like a BJT to make a large amount of current flow. The GGNMOS is very robust to a relatively long-term ESD, but is weak to protection from ESD introduced into the internal circuit before the actual discharge operation. The GCNMOS has a structure in which a silicide blocking layer is removed. The GCNMOS is very robust to a relatively short-term ESD, but is weak to a relatively long-term ESD. Elements of the ESD circuit are determined depending on the preference reference in the circuit design.
FIG. 1 is a circuit diagram explaining a conventional ESD circuit using normal diodes.
An input/output pad 110, an ESD circuit 120, and an internal circuit 130 are illustrated in FIG. 1.
The ESD circuit 120 protects the internal circuit 130 from ESD introduced through the input/output pad 110. The ESD circuit 120 includes first and second normal diodes D1 and D2 configured to transfer ESD introduced from the input/output pad 110 to a power supply voltage terminal VDD or a ground voltage terminal VSS, and a resistor R configured to drop an ESD voltage.
The sizes of the first and second normal diodes D1 and D2 and the resistor R may vary depending on design, but it is usual to design the first and second diodes D1 and D2 to have a relatively large size. For reference, if the resistor R has a very small resistance, the operation of protecting the internal circuit 130 from the ESD introduced through the input/output pad 110 is degraded. If the resistor R has a very large resistance, data loss may occur during the data input/output operation. Therefore, it is important to design the resistor to have an appropriate size.
Meanwhile, the semiconductor device undergoes a test operation before mass production in order to test whether the internal circuit 130 is protected from ESD introduced through the input/output pad 110 during a normal operation. In the test operation, it is usual to set all nodes to a floating state and apply ESD to only nodes corresponding to ESD intended to be tested.
In other words, when positively charged ESD is applied to the input/output pad 110, the power supply voltage terminal VDD is set to a floating state and a ground voltage is applied to the ground voltage terminal VSS. In this case, the positively charged ESD introduced from the input/output pad 110 is transferred through the first normal diode D1 to the power supply voltage terminal VDD, and then discharged to the ground voltage terminal VSS by a power clamp (not shown). Such a discharge operation is also performed in the normal operation, and the internal circuit 130 is protected from ESD by the above-described operation of the ESD circuit 120.
As the technologies have been advanced, the semiconductor devices have been reduced in size. The size reduction is a factor that can hold a dominant position in price competitiveness. However, the size reduction has reached a limit in recent years. The ESD circuit 120 must include the first and second diodes D1 and D2 and the resistor R in order to protect the internal circuit 130 from ESD, and it is difficult to reduce the sizes of the respective elements.